The present invention relates to a multiplier arrangement comprising a pair of input terminals to which analog phase information is provided. The multiplier arrangement receives a set of high-frequency local oscillator signals (LO1, LO2, LO3, LO4) which are 90 degrees in phase shifted with respect to each other and the multiplier arrangement generates, from the analog phase information and from the high-frequency local oscillator signals, components of a high-frequency phase vector (PV).
Multiplier arrangements are already known in the art, e.g. from the article “Trends in Silicon Radio Large Scale Integration: Zero IF Receiver! Zero I & Q Transmitter! Zero Discrete Passives!” by J. Sevenhans, B. Verstraeten and S. Taraborrelli, IEEE Communications Magazine, January 2000 Vol. 38, Nr. 1, pp 142-147. Therein, in FIG. 5 on page 144, a traditional Cartesian I and Q transmit modulator is shown, including two blocks indicated with an “X” as well as a device, indicated with a “+”. The two blocks denoted “X” are mixers in a traditional I/Q transmit modulator, each of them thereby receiving a respective pair of high frequency local oscillator signals, as well as a respective one of the Cartesian components of the analog phase information, namely sin(φ) and cos(φ). Each of them generates from its respective Cartesian component, as well as from its respective local oscillator signals, a corresponding component of a high-frequency phase vector. These two components are subsequently added in the block denoted “+”, to be considered as corresponding to the summing means of the multiplier arrangement under consideration.
A drawback of this prior art multiplier arrangement is that it consumes a lot of power, since both mixers are continuously active during the whole operation of this arrangement. Furthermore, a linear power amplifier is needed since these mixers themselves are performing also an image rejection operation. Linear power amplifiers, however, are very power consuming.